Adaptive Jitter Reduction in All Digital Symbol Timing Recovery Loops

In this paper, an adaptive jitter reduction technique is presented to substantially mitigate the tracking jitter of symbol timing recovery loops (STRLs) in all digital receivers and, hence, enhance the overall performance of the loop. This has been achieved by a structure utilizing a notch filter in a cascade arrangement with the loop filter to suppress the undesired frequency components and preserve the DC value at the output of the loop filter, which represents the trial value of the symbol timing error. Also, to improve the acquisition time of the loop, a dynamic gain control feedback path is added in the structure. A bit error rate (BER) performance close to theoretical results in presence of additive white Gaussian noise (AWGN), a very fast acquisition time and a low computational complexity have been achieved.